Date: 10/18/1986On October 18, 1986, Pyramid Technology Corporation registered the domain name, making it 29th .com domain ever to be registered.

Pyramid Technology Corporation was a computer company that produced a number of RISC-based minicomputers at the upper end of the performance range. It was based in the San Francisco Bay Area of California They also became the second company to ship a multiprocessor UNIX system (branded OSx), in 1985, which formed the basis of their product line into the early 1990s. Pyramid’s OSx was a dual-universe UNIX which supported programs and system calls from both 4.xBSD and AT&T’s UNIX System V.

Pyramid Technology was formed in 1981 by a number of ex-Hewlett-Packard employees, who were interested in building first-rate minicomputers based on RISC designs. In March 1995 Pyramid was bought by Siemens AG and merged into their Siemens Computer Systems US unit. In 1998 this unit was split, with the services side of the operation becoming Wincor Nixdorf. In 1999 Siemens and Fujitsu merged their computer operations to form Fujitsu Siemens Computers, and finally Amdahl was added to the mix in 2000. Pyramid Technology Corp. manufactures a 32-bit virtual memory super mini-computer for sale to engineering, scientific, and military applications. The company is engaged in the design, manufacture, marketing, and support of high-end, large-scale servers that deliver mainframe-class performance for the open enterprise client/server environment. The company is based in San Jose, California. Pyramid Technology Corp. was formerly a subsidiary of Siemens Nixdorf Informationssysteme AG.



The first Pyramid Technology series of minicomputers was released in August 1983 as the 90x superminicomputer, which used their custom 32-bit scalar processor running at 8 MHz. Although the architecture was marketed as a RISC machine, it was actually microprogrammed. It used a “sliding window” register model based on the Berkeley RISC processor, but memory access instructions had complex operation modes that could require many cycles to run. Many register-to-register scalar instructions were executed in a single machine cycle. Initially, floating point instructions were executed totally in microcode, although an optional floating point unit on a separate circuit board was released later. Microprogramming also allowed other non-RISC luxuries such as block move instructions.

Programs had access to 64 registers, and many instructions were triadic. Sixteen registers (registers 48 to 63) were referred to as “global registers” and they correspond to the registers of a typical CPU, in that they are static and always visible. The other 48 registers were actually the top of the subroutine stack. Thirty-two of them (0–31) were local registers for the current subroutine, and registers 32–47 were used to pass up to 16 parameters to the next subroutine called. During a subroutine call, the register stack moved up 32 words, so the caller’s registers 32–47 became the called subroutine’s registers 0–15. The return instruction dropped the stack by 32 words so return parameters would be visible to the caller in registers 32–47. The stack cache held 16 levels in the CPU and stack overflow and underflow was automatically handled by the microcode of the CPU. The programming model had two stacks, one for the register stack, and one for subroutine local variables. One grew up from a designated address in the middle of the address space, and the other grew down from the top of the user mode address space. The 90x could accommodate four memory boards, initially holding 1 MB each. This was considered to be a lot of memory at the time, but the RISC-like architecture resulted in bigger programs than earlier architectures so most machines were sold with the memory slots full. Fortunately, the 1 MB memory boards had RAM in sockets, so they could be upgraded to 4 MB units when bigger dynamic RAM devices became available shortly after the 90x’s initial release. The 90x competed with the Digital Equipment Corporation (DEC) VAX 11/780 which was the preferred platform for running UNIX in the early 1980s. The 90x processor benchmarked at roughly twice the speed of the VAX, and sold for about half the price. Pyramid was indirectly assisted by DEC’s reluctance to sell VAX machines without the VMS operating system, for which they charged a considerable amount of money. Many universities wanted to run UNIX rather than VMS, so Pyramid’s higher performance and lower price, coupled with artificial delivery delays or surcharges from DEC, helped them to make the risky decision to buy from a new manufacturer.

One of the 90x’s biggest advantages over the competition was its asynchronous serial port controller (the ITS or Intelligent Terminal Server) based on a 16-bit bit-slice processor. The ITS interfaced to 16 serial ports, and it could run them at very high speeds, using DMA to feed from daisy-chained output data blocks. A machine could have many ITSs installed, each one with its own I/O processor. Other machines at the time (including the 11/780) required CPU intervention every few bytes for interactive users, which added significantly to the system component of the CPU load. As a result, the 90x scored very well on benchmarks with a realistic amount of serial I/O. The disk and magnetic tape controllers were actually 16-bit third-party Multibus controllers fitted into a socket in a U-shaped bus-adapter board. Most early systems were delivered with the 470 MB Fujitsu Eagle disk drive and a slot-loading reel-to-reel streaming tape drive. The system also had an administrative processor (based on a Motorola 68000) that loaded the microcode from an 8″ floppy disk when the system was started. It was also able to run a suite of diagnostics over the system. It had a modem which allowed remote analysis by the manufacturer. The software run by the administrative processor was initially called the Totally Unrealistic Remote Diagnostic. This name was changed some years later. A minimal system was delivered in a single 19″ rack about 60″ high with the card cage in the bottom, the disk drive in the middle, the tape drive above it, then the 2 inch high control panel with a floppy disk drive and ignition key on the top. This was considered very compact at the time. At least one machine in Australia spend six months installed in a retired outdoor lavatory with an air-conditioner replacing the louvered window and the system console terminal sitting on top of the cabinet. Administration tasks were performed al-fresco. The only indicator on the control panel was an 8 segment bar graph LED display that displayed average CPU usage when the machine was running and a “Cylon Eye” pattern when the machine stopped unexpectedly. The machine was low enough that the console (a monochrome asynchronous terminal) could rest on top.


The 90x was fairly quickly followed by the 98x which was identical except that the processor clock speed was increased to 10 MHz. In late 1985 Pyramid released its first SMP system, 98x, running at 7 MHz. Several machines in the series were released, from the 1-CPU 9815 to the 4-CPU 9845, over a period of years from 1985 to 1987. The fully loaded 9845 ran at about 25 MIPS, a respectable figure for the era, though not competitive with high-end supercomputers.


Like many of the early multiprocessor vendors, Pyramid turned to “commodity” RISC CPUs when they started to become practical. Pyramid continued to use their own RISC design until the release of the MIServer S product line. Pyramid released a series of register window-based machines as a 9000 line follow on. These were known as the MIServer starting in 1989. They supported up to ten CPUs with performance of about 12 MIPS each. The MIServer was replaced in 1991/2 with the MIServerT and later followed up with the MIServer S and ES, Pyramid’s first R3000-based machine. The first machines in the series shipped with anywhere from 4 to 12 R3000s running at 33 MHz, with top-end performance around 140 MIPS. Later high-end MIServer ES machines had up to 24 CPUs, also at 33 MHz. The operating system for the MIPS based systems was DC/OSx, a port of AT&T System V Release 4 (SVR4).

Nile series

The release of the 150 MHz 64-bit R4400 led to the 2–16-CPU Nile series in late 1993. With each CPU capable of 92 MIPS, the Nile systems were true supercomputers. Their last product, the Reliant RM 1000, known internally as the Meshine, was just coming to market when Siemens bought them. The RM1000 was a massive parallel processing (MPP) computer. Each node ran its own instance of Reliant UNIX DC/OSx. This system had a two-axis mesh architecture. The RM1000 used software called ICF to manage the cluster interconnects. ICF went on to provide the cluster foundation in the PrimeCluster HA software which is still developed and available from Fujitsu Siemens.

Each compute node in the mesh used a single MIPS R10000 CPU, however enhancements to the RM1000 allowed for the NILE SMP machines to be included into the mesh as “fat” nodes. The compute nodes were physically installed in the HAAS-3 frames that shipped as drive arrays with the earlier Nile product. Each compute node controlled six SCSI disks as the primary controller and another six disks as a secondary controller. The frame with up to six compute nodes or four compute nodes and two Nile attach gateways was connected to neighboring frames with short ribbon cables. A HAAS-3 frame with compute nodes installed was called a cell. The cells locked together and could be stacked two high and end to end as far as space permitted. Four cells together were known as a ton and systems were referred to by the number of tons they contained. The largest mesh constructed at Pyramid was a test system containing 214 CPUs including four Nile SMP nodes. Although the RM1000 was eventually discontinued and not replaced by Siemens, customers who had large installations such as a large UK telecommunications company took a long time to find suitable replacements for these massively parallel systems due to their massive I/O and computing capabilities.